1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor apparatus, and more particularly, to a vertical-type semiconductor apparatus, and a fabrication method thereof.
2. Related Art
Semiconductor memory apparatuses are designed to fleet the demands on high integration, ultra miniaturization, or the like, and one of such apparatuses is a vertical-type semiconductor apparatus.
In the vertical-type semiconductor apparatus, a transistor used as a selection device of a memory cell is initially developed to have a vertical channel. The vertical transistor is fabricated in a surround type, all-around type, or the like.
FIG. 1 is a layout diagram illustrating a general vertical-type semiconductor apparatus, and FIGS. 2 and 3 are cross-sectional views illustrating the semiconductor apparatus of FIG. 1. Specifically, FIGS. 2 and 3 are cross-sectional views taken along lines X1-X2 of FIG.
Referring to FIGS. 1 and 2, a plurality of pillars 103 are formed on a semiconductor substrate 101. A gate insulating layer 105 is formed on an outer circumference of each pillar 103 to have a given height, and a gate conductive layer 107 is formed to surround the gate insulating layer 105. For separation between word lines, the gate conductive layer 107 is patterned as a line type in a first direction, for example, an X1-X2 direction.
A semiconductor substrate 101 below the pillar 103 serves as a common source region, and an upper portion of the pillar 103, which is not surrounded with the gate conductive layer 107, serves a drain region.
Operation voltages are to be applied to the gate conductive layer 107 and the common source region, and to this end, a gate contact region 109 and a source contact region 111 are defined.
In order to form a gate contact in the gate contact region 109, any one pillar formed in the gate contact region 109 is removed to form a gate contact hole after the gate conductive layer 107 is patterned in a word line direction. An insulating material is buried in the gate contact hole and then recessed.
A conductive material is buried on the recessed insulating material in the gate contact hole to form a gate contact 109A.
A source contact 111A may be formed by removing a structure formed on the semiconductor substrate 101 of the source contact region 111 to expose the semiconductor substrate 101, forming an insulating layer, forming a source contact hole exposing the semiconductor substrate 101, and burying a conductive material in the source contact hole.
An insulating material having a certain thickness is to exist between the gate contact 109A and the semiconductor substrate 101. That is, as illustrated in FIG. 2, the gate contact 109A is electrically coupled to the gate conductive layer 107, but insulated from the semiconductor substrate 101 as the common source region by the insulating material.
However, when the thickness of the insulating material remaining after the recess is not precisely controlled by an error on a process, the gate contact 109A is in contact with the silicon substrate 101 indicated by “A” of FIG. 3, and thus a short circuit occurs.